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Figure 26.2. DAC Bias Programming
Reference
Current
BIASPROG
HALFBIAS
Internal
bandgap
reference
DAC output
buffer
The minimum value of the BIASPROG bitfield of the DACn_BIASPROG register (i.e.
BIASPROG=0b0000) represents the minimum bias current. Similarly BIASPROG=0b1111 represents
the maximum bias current. The bias current defined by the BIASPROG setting can be halved by setting
the HALFBIAS bit of the DACn_BIASPROG register.
The bias current settings should only be changed while both DAC channels are disabled. The electrical
characteristics given in the datasheet require the bias configuration to be set to the default values, where
no other bias values are given.
26.3.4 Mode
The two DAC channels can act as two separate single ended channels or be combined into one
differential channel. This is selected through the DIFF bit in DACn_CTRL.
26.3.4.1 Single Ended Output
When operating in single ended mode, the channel 0 output is on DACn_OUT0 and the channel 1 output
is on DACn_OUT1. The output voltage can be calculated using Equation 26.2 (p. 368)
DAC Single Ended Output Voltage
V OUT = V DACn_OUTx - V SS = V ref x CHxDATA/4095
(26.2)
where CHxDATA is a 12-bit unsigned integer.
26.3.4.2 Differential Output
When operating in differential mode, both DAC outputs are used as output for the bipolar voltage. The
differential conversion uses DACn_CH0DATA as source. The positive output is on DACn_OUT1 and
the negative output is on DACn_OUT0. Since the output can be negative, it is expected that the data is
written in 2’s complement form with the MSB of the 12-bit value being the signed bit. The output voltage
can be calculated using Equation 26.3 (p. 368) :
DAC Differential Output Voltage
V OUT = V DACn_OUT1 - V DACn_OUT0 = V ref x CH0DATA/2047
(26.3)
where CH0DATA is a 12-bit signed integer. The common mode voltage is V DD /2.
26.3.5 Sine Generation Mode
The DAC contains an automatic sine-generation mode, which is enabled by setting the SINEMODE bit in
DACn_CTRL. In this mode, the DAC data is overridden with a conversion data taken from a sine lookup
table. The sine signal is controlled by the PRS line selected by CH0PRSSEL in DACn_CH0CTRL. When
the PRS line is low, a voltage of Vref/2 will be produced. When the line is high, a sine wave will be
2011-04-12 - d0001_Rev1.10
368
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